Discussion
Home ‣ Digital Electronics ‣ Digital Design Comments
- Question
Why is the Schmitt trigger needed in the 60-Hz TTL-level clock pulse generator?
Options- A. to provide a triangle wave
- B. to provide a sine wave
- C. to provide a rounded pulse waveform
- D. to provide a sharp pulse waveform
- Correct Answer
- to provide a sharp pulse waveform
- 1. Why would a delay gate be needed for a digital circuit?
Options- A. A delay gate is never needed.
- B. to provide for setup times
- C. to provide for hold times
- D. to provide for setup times and hold times Discuss
- 2. A 0.01-µF capacitor is recommended by TTL manufacturers for ________ the power supply.
Options- A. decoupling
- B. filtering
- C. rectifying
- D. grounding Discuss
- 3. How much setup time (ts) is required for the 74LS76?
Options- A. 5 ns
- B. 10 ns
- C. 20 ns
- D. 40 ns Discuss
- 4. Can the automatic RC circuit be used to set a flip-flop rather than reset the flip-flop?
Options- A. yes
- B. no Discuss
- 5. Setup time specifies:
Options- A. the minimum time the control levels need to be maintained on the inputs prior to the triggering edge of the clock in order to be reliably clocked into the flip-flop
- B. the maximum time interval required for the control levels to remain on the inputs before the triggered edge of the clock in order for the data to be reliably clocked out of the flip-flop
- C. how long the operator has to get the flip-flop running before the maximum power level is exceeded
- D. how long it takes the output to change states after the clock has transitioned Discuss
- 6. Look up the propagation delay from the clock to the output for the 7476. Are the HIGH-to-LOW and LOW-to-HIGH propagation delays the same?
Options- A. yes
- B. no, tPLH = 25 ns, tPHL = 40 ns
- C. no, tPLH = 40 ns, tPHL = 25 ns
- D. no, tPHL = 25 ns, tPLH = 40 ns Discuss
- 7. In the automatic reset circuit for a flip-flop, how long does it take the capacitor to completely charge?
Options- A. 1 time constant (RC)
- B. 2 time constants (RC)
- C. 5 time constants (RC)
- D. 10 time constants (RC) Discuss
- 8. A settable flip-flop's normal starting state when power is first applied to a circuit is always the ________ state.
Options- A. reset
- B. set
- C. toggle
- D. dual Discuss
- 9. What is the difference between setup time and hold time?
Options- A. Setup time occurs after the active clock edge, hold time occurs before the active clock edge.
- B. Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
- C. Setup time and hold time both occur at the active clock edge. Discuss
- 10. Which of the following circuit parameters would be most likely to limit the maximum operating frequency of a flip-flop?
Options- A. setup and hold time
- B. clock pulse HIGH and LOW time
- C. propagation delay time
- D. clock transition time Discuss
Digital Design problems
Search Results
Correct Answer: to provide for setup times and hold times
Correct Answer: decoupling
Correct Answer: 20 ns
Correct Answer: yes
Correct Answer: the minimum time the control levels need to be maintained on the inputs prior to the triggering edge of the clock in order to be reliably clocked into the flip-flop
Correct Answer: no, tPLH = 25 ns, tPHL = 40 ns
Correct Answer: 5 time constants (RC)
Correct Answer: set
Correct Answer: Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
Correct Answer: propagation delay time
Comments
There are no comments.More in Digital Electronics:
Programming
Copyright ©CuriousTab. All rights reserved.