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Home ‣ Digital Electronics ‣ Memory and Storage See What Others Are Saying!
  • Question

  • The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit?

    The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activi


  • Options
  • A. The Q0, Q2, and Q3 output lines are open; the chip is defective.
  • B. The Q1 line appears to be shorted to Vcc; replace the chip.
  • C. The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH.
  • D. The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced.

  • Correct Answer
  • The Q1 line appears to be shorted to Vcc; replace the chip. 

    • More questions

    • 1. The output pulse width for a 555 monostable circuit with R1 = 3.3 kΩ and C1 = 0.02 µF is ________.

    • Options
    • A. 7.3 µs
    • B. 73 µs
    • C. 7.3 ms
    • D. 73 ms
      • Discuss
    • 2. Which of the figures given below represents a NOR gate?


    • Options
    • A. a
    • B. b
    • C. c
    • D. d
      • Discuss
    • 3. What is one advantage to using a parallel-encoded (flash) ADC?

    • Options
    • A. less expensive
    • B. very fast conversion
    • C. less complicated circuit
      • Discuss
    • 4. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?


    • Options
    • A. a
    • B. b
    • C. c
    • D. d
      • Discuss
    • 5. In a multiplexer, the data select control inputs are responsible for determining which data input is selected to be transmitted to the data output line.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. The time required to complete a conversion cycle is called conversion time.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. When more than one IC is used to provide all the addressable locations in a memory, a technique called ________ is used to identify which IC is being accessed.

    • Options
    • A. address decoding
    • B. memory refresh
    • C. data encoding
    • D. memory paging
      • Discuss
    • 8. For the SOP expression , how many 1s are in the truth table's output column?

    • Options
    • A. 1
    • B. 2
    • C. 3
    • D. 5
      • Discuss
    • 9. A typical RAM will write (store data internally) whenever the Chip Select line is active and the Write Enable line is inactive.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. The TTL HIGH level source current is higher than the LOW level sinking current.

    • Options
    • A. True
    • B. False
      • Discuss

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