Discussion
Home ‣ Digital Electronics ‣ Memory and Storage Comments
- Question
FIFO is formed by an arrangement of ________.
Options- A. diodes
- B. transistors
- C. MOS cells
- D. shift registers
- Correct Answer
- shift registers
- 1. Address decoding for dynamic memory chip control may also be used for:
Options- A. controlling refresh circuits
- B. read and write control
- C. chip selection and address location
- D. memory mapping Discuss
- 2. What is the computer main memory?
Options- A. Hard drive and RAM
- B. CD-ROM and hard drive
- C. RAM and ROM
- D. CMOS and hard drive Discuss
- 3. Which is/are the basic refresh mode(s) for dynamic RAM?
Options- A. Burst refresh
- B. Distributed refresh
- C. Open refresh
- D. Burst refresh and distributed refresh Discuss
- 4. Which of the following is NOT a type of memory?
Options- A. RAM
- B. ROM
- C. FPROM
- D. EEPROM Discuss
- 5. Why is a refresh cycle necessary for a dynamic RAM?
Options- A. to clear the flip-flops
- B. to set the flip-flops
- C. The refresh cycle discharges the capacitor cells.
- D. The refresh cycle keeps the charge on the capacitor cells. Discuss
- 6. The time from the beginning of a read cycle to the end of tACS or tAA is referred to as:
Options- A. access time
- B. data hold
- C. read cycle time
- D. write enable time Discuss
- 7. Which of the following best describes static memory devices?
Options- A. memory devices that are magnetic in nature and do not require constant refreshing
- B. memory devices that are magnetic in nature and require constant refreshing
- C. semiconductor memory devices in which stored data will not be retained with the power applied unless constantly refreshed
- D. semiconductor memory devices in which stored data is retained as long as power is applied Discuss
- 8. To which pin on the RAM chip does the address decoder connect in order to signal which memory chip is being accessed?
Options- A. The address input
- B. The output enable
- C. The chip enable
- D. The data input Discuss
- 9. For the given circuit, what is the bit length of the output data word?
Options- A. 3
- B. 4
- C. 8
- D. 32 Discuss
- 10. What part of a Flash memory architecture manages all chip functions?
Options- A. I/O pins
- B. floating-gate MOSFET
- C. command code
- D. program verify code Discuss
Memory and Storage problems
Search Results
Correct Answer: chip selection and address location
Correct Answer: RAM and ROM
Correct Answer: Burst refresh and distributed refresh
Correct Answer: FPROM
Correct Answer: The refresh cycle keeps the charge on the capacitor cells.
Correct Answer: access time
Correct Answer: semiconductor memory devices in which stored data is retained as long as power is applied
Correct Answer: The chip enable
Correct Answer: 4
Correct Answer: floating-gate MOSFET
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