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  • Question
  • What is meant by parallel load of a shift register?


  • Options
  • A. All FFs are preset with data.
  • B. Each FF is loaded with data, one at a time.

  • Correct Answer
  • All FFs are preset with data. 


  • Shift Registers problems


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    • 1. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.

    • Options
    • A. 10111000
    • B. 10110111
    • C. 11110000
    • D. 11111100
    • Discuss
    • 2. On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.

    • Options
    • A. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
    • B. Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
    • C. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
    • D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0
    • Discuss
    • 3. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

    • Options
    • A. 1100
    • B. 0011
    • C. 0000
    • D. 1111
    • Discuss
    • 4. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

    • Options
    • A. 10011100
    • B. 11000000
    • C. 00001100
    • D. 11110000
    • Discuss
    • 5. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.

    • Options
    • A. 01110
    • B. 00001
    • C. 00101
    • D. 00110
    • Discuss
    • 6. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.

    • Options
    • A. 4 ?s
    • B. 40 ?s
    • C. 400 ?s
    • D. 40 ms
    • Discuss
    • 7. What does the output enable do on the 74395A chip?

    • Options
    • A. It determines when data can be loaded.
    • B. It forces all outputs to go HIGH.
    • C. It forces all outputs to go LOW.
    • D. It activates the three-state buffer.
    • Discuss
    • 8. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

    • Options
    • A. 11101011
    • B. 00010111
    • C. 11110000
    • D. 00000000
    • Discuss
    • 9. What is a transceiver circuit?

    • Options
    • A. a buffer that transfers data from input to output
    • B. a buffer that transfers data from output to input
    • C. a buffer that can operate in both directions
    • Discuss
    • 10. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.

    • Options
    • A. 1110
    • B. 0001
    • C. 1100
    • D. 1000
    • Discuss


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