Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Shift Registers
How much storage capacity does each stage in a shift register represent?
One bit
Two bits
Four bits (one nibble)
Eight bits (one byte)
Correct Answer:
One bit
← Previous Question
Next Question→
More Questions from
Shift Registers
What is a recirculating register?
A modulus-12 ring counter requires a minimum of ________.
A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.
An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.
The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?
If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?
What is the difference between a shift-right register and a shift-left register?
How would a latch circuit be used in a microprocessor system?
What are the three output conditions of a three-state buffer?
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments