Give a circuit to divide frequency of clock cycle by two?

Correct Answer: Pass input to XOR and give their outputs to OR gate, if your output is 0 both 8-bit signals are same OR Pass input to XNOR and give their outputs to AND gate, if your output is 1 both 8-bit signals are same

Correct Answer: TRUTH TABLE FOR HALF ADDER A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 INPLEMENTATION: For SUM, The two inputs A and B are given to XOR gate For Carry, The two inputs A and B are given to AND gate

Correct Answer: A SIPO and AND gate circuit can detect this sequenceThe output of SIPO is connected to a four input AND gate ,the third SIPO output should be connected through a NOT gateWhen the 1101 sequence is loaded in to the SIPO the AND output goes HIGH otherwise keeps LOW

Correct Answer: Use the concept of register-retiming divide the totla combinatorial delay in two segments such that individually the delay is less the clock period this can be done by inserting a flip-flop in the combinational path eg, clock period --- 5 ns total cominational delay ---- 7 then divide the 7ns path in two path of 4 or 3 (best resutls are obtained if delays are same for both path ie 35ns) by inserting a flip-flop in between

Correct Answer: In 8086 Carry flag, Parity flag, Ausiliary caarry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag

Correct Answer: Adders are generally of five types: 1Ripple Carry Adder: The Ripple carry adder(RCA) consists of a building block named Half Adder(HA) which is cascaded to form a Full Adder(FA) These buildingblocks HAs and FAs are also the building blocks of all types of addersThe n full adders are cascaded to form n bit RCA The full adder has three input pins(input Ai,input Bi,carryin Ci) and two output pins(Sum and Ci+1)Its equations are: Sum=Ai^Bi^Ci Ci+1=AiBi+BiCi+AiCi 2 Carry Lookahead Adder: The Carry Lookahead Adder(CLA) reduces the delay as that in RCA Let Gi=AiBi, and Pi=Ai^Bi, then Ci+1=Gi+PiCi The expressions for Sum and Ci+1 is then defined completely in terms of input pins rather wait for input carry to appear 3 Carry Select Adder: The carry select adder uses duplicate modules for each combination of input carry(ie 1 and 0)The multiplexers then select the appropriate sum and carry output according to the carry output of the preceding stages 4 Carry Skip Adder: The carry skip adder are as fast as carry lookahead adders which are the fastest adders but its spped decreases to about 20-30% if input operands are 64-bit or more In these adders we divide the input bit stream into various blocks and make use of two observations: -if each element of the two bit streams are unequal,ie Ai!=Bi than the carry input of the block is equal to the carry input -if each element of the two bit streams are equal,ie Ai=Bi than the carry input of the block is opposite of the carry input 5 Carry Save Adder: The carry save adder reduces the addition of three elements into addition of two elements,ie if you want sum of nine numbers it reduces it into sum of six numbers In first step the sum of three numbers is calculated without bothering for the carryDuring the second step only carry is calculated which is then added to the generated sum to give the required sum

Correct Answer: The basic expansion card types in A+ Hardware certification are ISA and PCI, ISA these can be used only on XT, AT and ATX boards The industry now considers ISA obsolate

Correct Answer: Level 1 cache is internal to the chip, Level 2 is external

Correct Answer: IEEE 1394 (Firewire) supports the maximum of 63 connected devices with speeds upto 400 Mbps

Correct Answer: Main Boot Record is located is sector 0, track 0, head 0, cylinder 0 of the primary active partition