Static RAM (SRAM) vs. Dynamic RAM (DRAM) What is the basic operational difference between SRAM and DRAM in terms of data retention?

Introduction / Context:
SRAM and DRAM are the two dominant volatile memory types in digital systems. Their cell structures create distinctly different behaviors for data retention, power, speed, and density. Understanding refresh is essential for system timing and power design.

Given Data / Assumptions:

• SRAM uses multi-transistor latch cells that hold state as long as power is present.
• DRAM stores charge on a tiny capacitor, which leaks over time.
• Refresh is a periodic read/restore action necessary for DRAM capacitors.

Concept / Approach:

Because DRAM charge decays, controllers must perform refresh cycles to read and rewrite each row before the charge falls below a readable threshold. SRAM cells, being bistable latches, do not need refresh; they maintain 0 or 1 continuously under power, enabling faster random access at the cost of area.

Step-by-Step Solution:

Verification / Alternative check:

Every DRAM datasheet specifies refresh intervals (e.g., all rows within 64 ms). SRAM datasheets do not contain refresh timing; their limits revolve around access time and power.

Why Other Options Are Wrong:

• Option A is the inverse of reality.
• Option B ignores fundamental architectural differences.

Common Pitfalls:

• Equating nonvolatility with “no refresh.” Both SRAM and DRAM are volatile; neither retains data when power is removed.

Final Answer:

Dynamic RAM must be refreshed, static RAM does not.