VHDL does require a special designation for an output with a feedback.

More Questions from Flip-Flops

• Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.
• Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.
• The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.
• A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.
• Pulse-triggered or level-triggered devices are the same.
• A latch can act as a contact-bounce eliminator.
• A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.
• When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.
• In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.
• PRESET and CLEAR inputs are normally synchronous.

Discussion & Comments