Question 1

Computer architecture – memory read cycle During a memory read operation, the central processing unit (CPU) obtains information from the addressed memory location. What exactly does the CPU fetch in this read cycle?

Accepted Answer

Introduction / Context: In basic computer architecture, every memory transaction is either a read or a write. Understanding what the CPU fetches during a memory read cycle clarifies the roles of address buses, data buses, and control lines and helps learners distinguish between instruction fetches and general data accesses. Given Data / Assumptions: The CPU issues a specific address on the address bus. The memory subsystem decodes this address and, when Read is asserted, places the contents of that address on the data bus. Whether the content represents an instruction opcode or user data depends on program flow, but electrically it is still data returned from memory. Concept / Approach: A memory read cycle transfers bits from memory to the CPU. The CPU provides the address; the memory provides the contents. The control line (often labeled RD or MEMR) indicates the direction of transfer. An instruction fetch is just a special case of a memory read where the addressed location holds an opcode. Step-by-Step Solution: CPU places the target address on the address bus.CPU asserts the memory Read control signal.The addressed memory cell drives its stored contents onto the data bus.CPU samples the data bus and latches the returned data into internal registers. Verification / Alternative check: Textbooks and timing diagrams show that during reads, data moves from memory to CPU; during writes, data moves from CPU to memory. The only thing memory returns is the stored content (data). Why Other Options Are Wrong: “a program instruction” is a type of data; it does not change the mechanism. “an address” is driven by the CPU to memory, not fetched from it. “all of the above” is inaccurate because the address is not fetched from memory during a read. Common Pitfalls: Confusing instruction fetch with a different bus operation; assuming addresses come from memory rather than from the CPU or a DMA master. Final Answer: data

Question 2

Interrupt handling strategies in computer systems An interrupt method that requires the CPU to test each peripheral device in sequence to determine the source is called ________.

Accepted Answer

Introduction / Context: Computers interface with multiple peripherals that may request service. How the CPU discovers which device raised an interrupt significantly affects latency and software complexity. Two common schemes are polled and vectored interrupts. Given Data / Assumptions: Multiple devices can signal a need for service. The CPU must identify the requesting device before running its service routine. In the described method, the CPU checks devices one by one. Concept / Approach: In polled I/O, the CPU executes a polling loop that queries each device’s status register in a fixed order. The first device reporting a pending request is then serviced. In contrast, vectored interrupts provide a hardware-supplied vector that directly identifies the device and entry point for the service routine. Step-by-Step Solution: On interrupt, push context and enter a common handler.Iterate through device status registers in sequence.When a status bit indicates service required, branch to the corresponding ISR.Clear the request and restore context upon completion. Verification / Alternative check: Any architecture reference that describes polled interrupt service shows a loop over device flags; vectored service avoids this by using a hardware-provided address. Why Other Options Are Wrong: “vectored I/O” provides an immediate vector, no sequential testing. “programmed interrupt” is not a standard term for this behavior. “interrupt-driven I/O” is generic and can be vectored or polled. Common Pitfalls: High interrupt latency when many devices are polled; missing priority handling; forgetting to clear the source flag causing repeated servicing. Final Answer: polled I/O

Question 3

Processor instruction categories Instructions that allow direct control of the processor's condition flags and operating state (for example, enabling/disabling interrupts) are called ________ instructions.

Accepted Answer

Introduction / Context: Instruction sets are commonly grouped into categories: data transfer, arithmetic/logic, control flow, and processor control. Understanding these groups helps decode what each instruction affects: memory/registers, ALU results, branching, or processor state/flags. Given Data / Assumptions: We are focusing on instructions that modify flags or CPU state. Examples include setting/clearing interrupt enables, adjusting stack pointers, or explicit flag manipulation. The question asks for the general category name. Concept / Approach: Processor control instructions affect the CPU environment rather than user data. They may set the interrupt flag, clear carry/overflow, change privilege states (on some CPUs), or enter low-power modes. They are distinct from arithmetic/logic operations that might incidentally change flags as a byproduct. Step-by-Step Solution: Identify instruction purpose: does it alter CPU control state/flags?Group such instructions under the processor control category.Differentiate from ALU operations whose primary purpose is data computation.Conclude that the correct category is “processor control.” Verification / Alternative check: Consult any ISA reference (e.g., x86, ARM) that lists instructions like STI/CLI (x86) or CPS/SEI/CLI (microcontrollers) under system/processor control. Why Other Options Are Wrong: “data transfer” moves data among registers/memory. “arithmetic” computes results in the ALU. “bit manipulation” changes bits in operands, not CPU control state. Common Pitfalls: Confusing incidental flag updates from arithmetic with explicit flag-control instructions; overlooking privilege restrictions on some control instructions. Final Answer: processor control

Question 4

Control-flow classification of instructions The instructions JNZ (jump if not zero), JA (jump if above), and LOOP are all part of which instruction type?

Accepted Answer

Introduction / Context: Control-flow instructions alter the normal sequential execution of programs. By testing flags or counters and changing the instruction pointer, they implement loops, branches, and subroutine calls—core mechanisms for decision making and iteration. Given Data / Assumptions: JNZ branches based on the zero flag. JA branches based on comparison results (e.g., carry/zero flags for unsigned comparisons). LOOP decrements a counter and branches while it is nonzero. Concept / Approach: The common property is redirection of execution flow depending on conditions or counters. These are therefore categorized as loops and jumps (also called branch/control transfer instructions). Step-by-Step Solution: Recognize condition evaluation via flags (JNZ, JA).Identify iterative control via a counter (LOOP).Classify them under control-flow: loops and jumps.Confirm none of them moves data or performs arithmetic on general data. Verification / Alternative check: ISA manuals list these under conditional/unconditional branch and loop categories rather than data or arithmetic. Why Other Options Are Wrong: Data transfer moves operands; arithmetic changes numerical values; bit manipulation changes operand bits—none inherently alter the instruction pointer like branch/loop instructions. Common Pitfalls: Confusing flag-setting arithmetic with the subsequent branch that reads those flags; mixing up signed vs. unsigned branch conditions. Final Answer: Loops and jumps

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