In an asynchronous RS latch (active-high inputs), what happens when S is high and R is low, and what happens when S is low and R is high, with respect to the output state?

Introduction / Context:
The RS (Set-Reset) latch is a fundamental storage element in digital electronics. Understanding its truth table is essential for designing state machines and debouncing inputs. This question checks the effect of specific input combinations on the output Q.

Given Data / Assumptions:

• Asynchronous RS latch with active-high inputs.
• S = 1, R = 0 implies a set request.
• S = 0, R = 1 implies a reset request.
• We assume the invalid case S = 1, R = 1 is not part of this prompt.

Concept / Approach:
Use the canonical RS latch behavior: S drives Q high (set), R drives Q low (reset), and S = R = 0 holds the previous state. Map the stated input pairs to their outcomes on Q.

Step-by-Step Solution:

Verification / Alternative check:
Consult the RS truth table: S=1,R=0 → Q(next)=1; S=0,R=1 → Q(next)=0. This directly validates the result.

Why Other Options Are Wrong:

• No change, set: first part is false; S=1 forces a change.
• Race, high: 'race' does not describe this stable input combination.
• set, reset: wording does not match the blanks; first blank must be the resulting level (high).
• None of the above: incorrect because a correct mapping exists.

Common Pitfalls:
Confusing level descriptions ('set' vs 'high') and assuming synchronous behavior where clocking is required. RS latch acts immediately on inputs.

Final Answer:
high, reset