CPLD configuration memory — volatility characteristic A complex programmable logic device (CPLD) typically uses which type of on-chip configuration memory so that the user design is retained when power is removed?

Introduction / Context:
CPLDs and FPGAs differ notably in how they store configuration. Classic CPLDs employ nonvolatile technologies (EEPROM/flash/antifuse) that retain user logic without external configuration memory, enabling instant-on behavior and simplified system design compared to many SRAM-based FPGAs that require bitstream loading on power-up.

Given Data / Assumptions:

• CPLD families are commonly flash- or EEPROM-based.
• Nonvolatile storage retains configuration without power.
• Some modern FPGAs are SRAM-based and volatile (not the case for typical CPLDs).

Concept / Approach:
Because CPLDs target glue logic and deterministic startup, nonvolatile configuration is preferred. The device powers up directly into the user-defined behavior with minimal latency and no need for an external configuration ROM or processor to load a bitstream.

Step-by-Step Reasoning:

Verification / Alternative check:
Datasheets for common CPLD families (e.g., Xilinx CoolRunner, Intel/Altera MAX) state nonvolatile configuration using flash/EEPROM cells, confirming persistence across power cycles.

Why Other Options Are Wrong:

• volatile: describes SRAM-based architectures, more common in FPGAs.
• EPROM: a specific technology once used in PLDs; while nonvolatile, CPLDs typically use EEPROM/flash with electrical erase, not UV EPROM.
• “volitile EPROM”: misspelled and contradictory; EPROM is nonvolatile.
• battery-backed SRAM: not typical for CPLDs.

Common Pitfalls:

• Assuming all programmable logic behaves like SRAM-based FPGAs; CPLDs are different.

Final Answer:
nonvolatile