When a CPU fetches an instruction from memory, on which bus do the instruction bits (binary code) appear as they are transferred into the processor?

Introduction / Context:
Understanding the CPU–memory interface clarifies how instructions and data move through a computer. During an instruction fetch, the processor reads an instruction word from memory; knowing which bus carries the bits helps in diagnosing hardware issues and studying computer architecture.

Given Data / Assumptions:

• The CPU issues an address for the next instruction.
• Memory responds by placing the instruction word on a data bus.
• Standard split between address and data buses.

Concept / Approach:
The processor places the instruction address on the memory address bus. In response, the memory subsystem puts the instruction bits onto the memory data bus, which the CPU samples to load the instruction register. The I/O buses are used for peripheral addressing/data—not for main memory instruction fetches.

Step-by-Step Solution:
1) Identify the fetch sequence: address out, data in. 2) Map “data in from memory” to the memory data bus. 3) Exclude I/O-specific buses and directional labels that don’t match memory fetch semantics. 4) Select “Memory data bus.”

Verification / Alternative check:
Instruction cycle diagrams show address lines driven by CPU and read data returning over the data bus to the instruction register, confirming the answer.

Why Other Options Are Wrong:
I/O address bus: for peripherals, not memory fetch. Input/output data bus labels are ambiguous and not architectural terms for the memory path. “None” is wrong because the memory data bus is standard.

Common Pitfalls:
Confusing logical direction with bus naming; even though data flows into the CPU, it is still called the memory data bus in many textbooks.

Final Answer:
Memory data bus