An 8-bit serial-in/serial-out (SISO) shift register is clocked at 2 MHz. Assuming one bit shifts per clock, what total time delay (td) does the register introduce from input to output?

Introduction / Context:
Serial-in/serial-out (SISO) shift registers delay data by shifting one bit per clock. They are commonly used for timing alignment, serialization, and simple delay lines in digital systems. The total delay equals the number of stages multiplied by the clock period because a bit must traverse each flip-flop stage sequentially.

Given Data / Assumptions:

• Register length: 8 bits (8 stages).
• Clock frequency fclk = 2 MHz.
• Each clock shifts data by exactly one stage.
• No additional pipeline or combinational delay is considered.

Concept / Approach:
The time delay through an N-bit SISO register is td = N / fclk. This follows because each shift moves the bit by one stage every clock period T = 1 / fclk, and the bit must advance through N stages to appear at the output.

Step-by-Step Solution:
1) Compute the clock period: T = 1 / fclk = 1 / (2 × 10^6) seconds = 0.5 µs.2) The number of stages N = 8.3) Total delay td = N × T = 8 × 0.5 µs = 4.0 µs.4) Therefore, the correct delay is 4 µs.

Verification / Alternative check:
Formula check: td = N / fclk = 8 / (2 × 10^6) s = 4 × 10^−6 s = 4 µs. This matches the stage-by-stage reasoning above.

Why Other Options Are Wrong:
16 µs and 8 µs: would correspond to a slower clock or more stages.2 µs and 1 µs: imply fewer stages or a faster clock than specified.

Common Pitfalls:
Forgetting that the delay scales linearly with the number of stages, or mixing up parallel and serial shifting behavior. Another common mistake is using frequency directly instead of converting to the period before multiplying by the number of stages.

Final Answer:
4 µs