SISO register timing – loading nibble 1100 (LSB first) A 4-bit serial-in/serial-out shift register is initially 0000. You wish to store 1100 with right-most bit first. What 4-bit pattern is present after the second clock pulse?

Introduction / Context:
With a cleared SISO register, early input bits may not yet be visible in the upper positions. Recognizing the serial order and the number of elapsed clocks is crucial to predict intermediate states.

Given Data / Assumptions:

• Register width: 4 bits, initial = 0000.
• Target nibble: 1100, right-most bit first → input sequence = 0, 0, 1, 1.
• Right shift; serial input enters MSB each clock.

Concept / Approach:
Feed the first two bits (both zeros) and observe that shifting zeros into a cleared register keeps it at zero for these first two steps. Only when ones start entering will the MSB become 1 on later clocks.

Step-by-Step Solution:
Clock 1 (in=0): 0000 → 0000.Clock 2 (in=0): 0000 → 0000.Therefore after two clocks, content remains 0000.

Verification / Alternative check:
Continue two more clocks to see the progression: Clock 3 (in=1): 1000; Clock 4 (in=1): 1100. This confirms the intermediate 0000 at the second clock.

Why Other Options Are Wrong:
1100 / 0011 / 1111 / 1000: These require more than two clocks or a different shift direction/serial entry point.

Common Pitfalls:
Assuming the desired final nibble appears immediately; under-counting clock pulses; mixing left-shift with right-shift behavior.

Final Answer:
0000