Bus pin minimization on 8085: to reduce IC pin count, does the 8085 multiplex address and data on the same physical lines (AD0–AD7) using an address latch?

Introduction / Context:
Chip packaging limits push designers to share pins across functions. The Intel 8085 is a classic example: it multiplexes low-order address bits and data on the same eight pins to keep the package small and cost-effective.

Given Data / Assumptions:

• 8085 uses pins AD0–AD7 for address/data multiplexing.
• ALE (Address Latch Enable) strobes an external latch to capture the low address byte.
• High address bits (A8–A15) are on dedicated pins.

Concept / Approach:
During the beginning of a machine cycle, AD0–AD7 carry the low-order address bits (A0–A7). ALE goes high to latch these into an external address latch (e.g., 74HC373). After latching, the same AD pins switch function to carry data (D0–D7) for the remainder of the cycle. This time-division sharing saves eight pins while preserving full functionality.

Step-by-Step Solution:

Verification / Alternative check:
Timing diagrams in 8085 references show ALE transitions and AD line role switching within a machine cycle.

Why Other Options Are Wrong:
Does not apply: contradicts published bus operation. Tying it to DMA or 16-bit CPUs is incorrect: this is a feature of the 8-bit 8085.

Common Pitfalls:
Forgetting to add the external latch in hardware designs; mis-timing ALE in simulations.

Final Answer:
Applies