Control vs. data buses: do the control bus and memory devices “share a bidirectional bus,” or are control signals generally unidirectional lines coordinating reads/writes alongside a separate bidirectional data bus?

Introduction / Context:In a classic microprocessor architecture, three buses cooperate: address (usually unidirectional), data (bidirectional), and control (directional lines for timing/qualification). This question corrects a common misconception that control and memory “share a bidirectional bus.”

Given Data / Assumptions:

• Control lines include RD, WR, IO/M, ALE, CS, READY, etc.
• Data bus carries payload bytes in both directions.
• Address bus selects the target location or device.

Concept / Approach:The control bus is not a unified bidirectional data path. It consists of distinct signals, each with a defined direction: for example, RD and WR are CPU outputs that indicate read or write. Chip Select (CS) is usually driven from decoding logic to the memory/peripheral. Data actually flows on the data bus, which is bidirectional. Therefore, the statement that “control bus and memories share a bidirectional bus” conflates roles: control signals coordinate the transfer; they are not the medium that carries data both ways.

Step-by-Step Solution:

Verification / Alternative check:Pinout tables show data lines as bidirectional and control lines as outputs/inputs with defined roles, not a shared bidirectional channel.

Why Other Options Are Wrong:“Applies” misrepresents bus functions. DMA and tri-state details do not change the conceptual separation of control versus data pathways.

Common Pitfalls:Thinking “bus” always implies a single shared set of lines; overlooking that control is a set of coordination signals, not a data path.

Final Answer:Does not apply (control lines direct transactions; data bus is separate and bidirectional)