Memory technologies: Which type of semiconductor memory uses a single MOSFET (1T) together with a storage capacitor as its basic memory cell structure?

Introduction / Context:
Digital systems rely on several memory technologies, each with distinct cell structures, speed, density, and power behavior. Understanding which memory uses a MOSFET plus a capacitor as its storage element is fundamental when comparing RAM choices for microcontrollers, processors, and SoCs.

Given Data / Assumptions:

• We compare common memory categories: SRAM, DRAM, ROM (mask/OTP/EEPROM are variations of nonvolatile storage).
• The question asks specifically about the composition of the memory cell.
• Focus on mainstream, textbook cell implementations.

Concept / Approach:
Dynamic random-access memory (DRAM) stores each bit as charge on a small capacitor isolated by a single MOSFET—commonly called a 1T1C (one-transistor, one-capacitor) cell. Because charge leaks, DRAM requires periodic refresh. Static RAM (SRAM) uses a bistable latch made of cross-coupled transistors (typically six transistors per bit in CMOS 6T SRAM) and does not need refresh while powered. ROM stores bits in fixed devices or connections and does not use a MOSFET-capacitor pair to represent a charged state that must be refreshed.

Step-by-Step Solution:

Verification / Alternative check:
Block diagrams of DRAM show word lines controlling access transistors and bit lines connected to sense amplifiers; the cell schematic clearly depicts the MOSFET-capacitor pair. SRAM schematics show cross-coupled inverters and access transistors without any explicit storage capacitor.

Why Other Options Are Wrong:

• SRAM: Uses 6T latch cells, not a capacitor-based charge store.
• ROM: Data is fixed in structure (mask/fuse/floating gate), not stored as a leaky capacitor charge.
• DROM: Not a standard category; sometimes used informally, but not the 1T1C cell type.

Common Pitfalls:
Confusing DRAM refresh behavior with SRAM, or assuming any MOS memory uses storage capacitors; only DRAM's data bit depends on capacitor charge that must be periodically restored.

Final Answer:
DRAM