Memory timing fundamentals: The access time t_acc (read access time) of a memory IC is primarily governed by which internal feature of the chip?

Introduction / Context:
Access time (t_acc) is one of the key figures of merit for memory ICs, indicating how quickly valid data appears at the outputs after a stable address is applied. Knowing the internal factors that dominate t_acc helps engineers choose appropriate memories for timing-critical designs.

Given Data / Assumptions:

• t_acc is defined from address valid to data valid.
• Applies to ROMs, SRAMs, and DRAMs (ignoring refresh for the basic definition).
• We focus on core contributors inside the chip rather than board-level effects.

Concept / Approach:
Once an external address is presented, the internal address decoder must resolve which wordline/bitline to select. The propagation through the address decoder tree and the subsequent bitline/sense-amplifier activation dominate the delay to valid data. Volatility (whether data is retained without power) does not intrinsically determine instantaneous access time; many volatile SRAMs are faster than nonvolatile memories, and DRAM t_acc depends on array, sense-amp, and decoder design rather than the mere property of being volatile.

Step-by-Step Solution:

Verification / Alternative check:
Vendor timing diagrams show t_AA or t_OE paths dominated by decode and sense delays. Design notes often optimize decoder trees to reduce access time, independent of whether the memory is volatile.

Why Other Options Are Wrong:

• Internal address buffer: Contributes small input conditioning delay; not the dominant factor.
• Volatility: A retention property, not a timing mechanism.
• Decoder and volatility: Volatility adds no direct delay component to the read path.

Common Pitfalls:
Equating technology class (SRAM/DRAM/Flash) with instant speed; real access time comes from decode depth, array RC, and sense-amp design.

Final Answer:
internal address decoder