Successive-approximation ADC timing For an 8-bit successive-approximation (SAR) analog-to-digital converter clocked at 20 kHz, what is the maximum conversion time per sample (assume 1 comparison per bit and ignore minor overhead)?

Introduction / Context:
A successive-approximation (SAR) ADC performs one binary search step per bit to decide the output code. The conversion time is tied directly to the ADC clock period and the number of bits, so being able to compute the worst-case conversion time is a core practical skill in data acquisition and embedded systems.

Given Data / Assumptions:

• N = 8 bits.
• Clock frequency f_clk = 20 kHz.
• Ideal SAR timing: 1 clock per comparison, so conversions require approximately N clocks.
• Minor overheads (track/hold, start, end) are ignored as directed.

Concept / Approach:
For a SAR converter, conversion_time ≈ N * T_clk, where T_clk = 1 / f_clk. Each bit decision takes one clock (trial via the internal DAC and comparator), so an 8-bit decision takes 8 clocks in the worst case.

Step-by-Step Solution:
Compute clock period: T_clk = 1 / 20,000 = 50 µs.Multiply by number of bits: T_conv ≈ 8 * 50 µs.T_conv ≈ 400 µs.Convert to milliseconds: 400 µs = 0.4 ms.

Verification / Alternative check:
Rule of thumb: a SAR ADC roughly needs as many clock cycles as bits. For 8 bits at 20 kHz, 20,000 / 8 ≈ 2,500 samples per second, giving 0.4 ms per conversion, which matches the calculation above.

Why Other Options Are Wrong:

• 12.8 ms and 6.4 ms: These imply far more than 8 cycles, inconsistent with SAR behavior.
• 0.05 ms (50 µs): That is only a single clock period, not 8 periods.

Common Pitfalls:

• Forgetting that SAR uses one comparison per bit, not per code.
• Confusing sampling rate with clock rate; sampling rate is clock rate divided by cycles per conversion.

Final Answer:
0.4 ms