The TTL HIGH level source current is higher than the LOW level sinking current.

More Questions from Integrated-Circuit Logic Families

• Usually P-MOS and N-MOS circuits are identical with the exception of the voltage polarities.
• The time it takes for a square wave to go from 10% to 90% of its voltage level is called propagation delay.
• A common means for measuring and comparing the overall performance of an IC family is the speed-power product.
• The noise margin for TTL is 0.8 V.
• The data sheet for the 74 series of TTL ICs shows that Vcc has a range of 4.5 V to 5.5 V.
• The dc noise margins calculated using the proper values from a standard TTL data sheet are the worst-case margins. The typical dc noise margins are usually somewhat higher.
• The logic family with the highest maximum clock frequency is HS-TTL.
• ECL gates are noted for their high frequency capability and small output voltage swing.
• The upper transistor of a totem-pole output is OFF when the gate output is low.
• The major advantage of TTL logic circuits over CMOS is lower propagation delay.

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