Transistor load line intuition (Q-point movement): As the operating point (Q point) slides along a fixed DC load line, how does the collector-to-emitter voltage behave when the collector current changes?

Introduction / Context:
A DC load line on the I_C–V_CE plane represents the constraint V_CE = V_CC − I_C * R_C for a given supply and collector resistor. The Q point is where device characteristics meet this line. Understanding how V_CE and I_C trade off along the line is fundamental for biasing and avoiding saturation/cutoff in amplifiers.

Given Data / Assumptions:

• Fixed V_CC and collector resistor R_C.
• Operating point varies along the straight load line.
• Small-signal effects ignored; purely DC relation considered.

Concept / Approach:
From V_CE = V_CC − I_C * R_C, V_CE is an affine decreasing function of I_C. Therefore, when I_C decreases, the subtracted term I_CR_C becomes smaller, so V_CE increases. Conversely, when I_C rises, V_CE drops, approaching saturation at low V_CE.

Step-by-Step Solution:
Write the load-line equation: V_CE = V_CC − I_CR_C.Treat V_CC and R_C as constants.Differentiate or reason: dV_CE/dI_C = −R_C < 0 → V_CE decreases as I_C increases.Therefore, if current decreases, voltage increases.

Verification / Alternative check:
Plot the endpoints: at I_C = 0, V_CE = V_CC (top-right). At V_CE = 0, I_C = V_CC/R_C (bottom-left). Movement along the line confirms the inverse relationship.

Why Other Options Are Wrong:
(b) V_CE cannot remain constant if I_C varies along a fixed line. (c) Claims the opposite trend. (d) The load line is a single straight relation; only one monotonic trend exists.

Common Pitfalls:
Confusing AC load lines or dynamic curves; overlooking saturation and cutoff limits.

Final Answer:
Voltage increases when current decreases.