J–K flip-flop configured as a D-type: If a logic signal D is applied to the J input and its complement D̄ is applied to the K input, a J–K flip-flop behaves as which device?

Introduction / Context:
J–K flip-flops are versatile because appropriate input conditioning can emulate other flip-flop types. One common technique wires the inputs so the device samples a single data line D effectively, reproducing D flip-flop behavior. Recognizing this mapping simplifies design when only J–K elements are available.

Given Data / Assumptions:

• Connections: J = D and K = D̄.
• Edge-triggered J–K flip-flop with proper setup/hold respected for D.
• No asynchronous overrides are active.

Concept / Approach:
From the J–K characteristic table: J = 1, K = 0 sets Q to 1; J = 0, K = 1 resets Q to 0; J = K = 0 holds; J = K = 1 toggles. With J tied to D and K tied to D̄, the pair (J,K) always forms either (1,0) when D = 1 or (0,1) when D = 0. Thus, at each valid clock edge, Q_next equals D, which is exactly the behavior of a D flip-flop.

Step-by-Step Solution:

Verification / Alternative check:
Implement the wiring in a simulator and apply a data waveform to D with clean edges relative to the clock. Observe Q tracks D on active edges exactly like a DFF. This is a classic textbook equivalence used in lab exercises.

Why Other Options Are Wrong:

• S–C or gated S–C: These are not standard flip-flop names and do not match the described mapping.
• TOGGLE or T with enable: Toggling would require J and K both tied high, not complementary to a data line.

Common Pitfalls:
Failing to maintain D stable around the clock edge (setup/hold violations); miswiring complements leading to unintended toggling; leaving inputs floating, which can cause unpredictable behavior.

Final Answer:
D flip-flop