Shift-register timing: For an input pulse train with clock period T, what total delay is produced by an n-stage shift register?

Introduction / Context:
Shift registers move data one stage per clock, creating predictable time delays in serial data paths, serializers/deserializers, and digital timing circuits. Knowing the relationship between the number of stages and total delay is essential for timing closure and interface design.

Given Data / Assumptions:

• Clock period: T (seconds per clock).
• Register length: n stages (each stage is typically a flip-flop).
• Data advances one stage per active clock edge.

Concept / Approach:
Each stage adds one clock-period delay because a bit placed at the input requires one clock to move into the first stage, another to move to the second, and so on. After n clocks, the bit emerges at the output of the nth stage, yielding a total delay proportional to the number of stages.

Step-by-Step Solution:
At time 0, inject the first input bit.After 1 clock (T), the bit occupies stage 1.After 2 clocks (2T), it occupies stage 2.…After n clocks (nT), it appears at the output of stage n.

Verification / Alternative check:
Simulate or sketch a timing diagram for a 3-stage register: the bit emerges after 3 clock cycles → total delay = 3T, confirming the general nT formula.

Why Other Options Are Wrong:
(n − 1)T and (n + 1)T underestimate or overestimate the progression by one cycle; 2nT doubles the actual time without basis.

Common Pitfalls:
Confusing pipeline latency with throughput; although latency is nT, once filled, a new bit exits each clock cycle.

Final Answer:
nT