Flip-Flops and Timers problems
- 1. A D-type flip-flop is constructed by connecting an inverter between the Set and Clock terminals.
Options- A. True
- B. False Discuss
Correct Answer: False
- 2. When the S and the R inputs are both HIGH the output of an S-R NOR latch will be unpredictable.
Options- A. True
- B. False Discuss
Correct Answer: True
- 3. J-K flip-flops are often used as switch debouncers.
Options- A. True
- B. False Discuss
Correct Answer: False
- 4. The J-K flip-flop eliminates the RACE state when both the J and K inputs are HIGH.
Options- A. True
- B. False Discuss
Correct Answer: True
- 5. Edge-triggered flip-flops must have _________.
Options- A. very fast response times
- B. at least two inputs to handle rising and falling edges
- C. a positive-transition pulse generator
- D. a negative-transition pulse generator Discuss
Correct Answer: a positive-transition pulse generator
- 6. The S-R, D-type, and J-K flip-flops are all examples of _________________.
Options- A. astable multivibrators
- B. bistable multivibrators
- C. monostable multivibrators
- D. tristable multivibrators Discuss
Correct Answer: bistable multivibrators
- 7. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be _________ ms.
Options- A. 3
- B. 7
- C. 10
- D. 13 Discuss
Correct Answer: 13
- 8. An S-R NAND latch with both of its inputs LOW has an output that is _____________.
Options- A. unpredictable
- B. floating
- C. HIGH
- D. LOW Discuss
Correct Answer: unpredictable
- 9. If an input is activated by a signal transition, it is _____________.
Options- A. edge-triggered
- B. toggle-triggered
- C. clock-triggered
- D. noise-triggered Discuss
Correct Answer: edge-triggered
- 10. The toggle condition in a master-slave J-K flip-flop means that Q and
will switch to their ________ state(s) at the _____________________.
Options- A. inverted, positive clock edge
- B. quiescent, negative clock edge
- C. opposite, active clock edge
- D. reset, synchronous clock edge Discuss
Correct Answer: opposite, active clock edge
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