PISO (parallel-in serial-out) behavior — a 4-bit PISO shift register loads 4 bits in parallel; on each active clock edge it shifts the data to the ______ by ______ position(s) per clock.

Introduction / Context:
Shift registers convert between parallel and serial forms of data. A PISO register loads a multi-bit word and then shifts it out serially. Designers must know the shift direction and how many bit positions change per clock to interface correctly with serializers and communication lines. This question targets that understanding.

Given Data / Assumptions:

• 4-bit PISO register with typical right-shift convention (MSB first).
• One active clock edge causes a single shift event.
• No bidirectional or dual-edge special modes are assumed.

Concept / Approach:
Most PISO ICs are designed to shift one position per clock edge, moving the stored bits toward the serial output. The default convention in many families is right shifting (moving MSB toward the serial-out pin). Although some devices can be configured for left shift, the standard reference case is one position per clock to the right, serializing one bit at a time.

Step-by-Step Solution:

Verification / Alternative check:
Reference timing diagrams of standard parts (e.g., 74HC165) confirm one-bit-per-clock serialization with a right-shift convention. Functional truth tables illustrate the movement clearly.

Why Other Options Are Wrong:

• Right, two / Left, one / Left, three: Do not reflect the standard single-position-per-clock behavior and/or shift direction of common PISO devices.

Common Pitfalls:
Confusing PISO with SIPO (serial-in parallel-out) parts; mixing up MSB-first vs LSB-first conventions between different device families or protocols.

Final Answer:
Right, one.