Parity systems: “In a parity generator circuit, an error is signaled on an error indicator.” This statement is ________.

Introduction / Context:
Parity subsystems often include both generation and checking functions, sometimes within the same integrated circuit. However, the roles are distinct: the generator creates a parity bit from data; the checker compares received data and parity to detect errors. This question probes whether you can distinguish those responsibilities.

Given Data / Assumptions:

• Parity generator: Computes parity bit from local data (transmit side).
• Parity checker: Examines incoming data plus parity to detect mismatches.
• Some ICs combine both functions, but the logic blocks remain conceptually separate.

Concept / Approach:
Only the checker asserts an error indicator because it performs a comparison between expected parity (recomputed from received data) and the received parity bit. A pure generator does not perform comparison and therefore has no basis to assert an error flag. Confusion arises because catalog parts may be titled “parity generator/checker.”

Step-by-Step Solution:

Verification / Alternative check:
Examine block diagrams of common parts (e.g., parity generator/checker devices): separate logic blocks are shown for generation and checking, with the error output present on the checker side only.

Why Other Options Are Wrong:

• Correct/only for even parity/with specific frames/with CRC: All imply a generator signals errors, which it does not. CRC is unrelated to a simple parity generator’s function.

Common Pitfalls:
Assuming “generator” and “checker” are interchangeable; overlooking that error detection requires comparison between expected and actual parity, which a generator does not perform.

Final Answer:
Incorrect