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Programmable Logic Device
The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.
True
False
Correct Answer:
False
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Programmable Logic Device
VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.
The JTAG signals are named TDI, TDO, TMS, and TCK.
A GAL is a programmable/reprogrammable PAL.
A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.
Schematic capture is a process performed by PLD software.
An expensive form of programmable logic is SPLD.
The GAL16V8 has eight dedicated input pins.
PLDs did not gain widespread acceptance with digital until the mid-1980s, when a device called a PAL was introduced.
In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.
Xilinx software uses triangular symbols called buffers to define pins as input or output.
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