8086 Bus Cycle: Match (BHE, A0) to Data Transfer Width and Addressing List I (BHE, A0) A. 0, 0 B. 0, 1 C. 1, 0 D. 1, 1 List II (What is read/written) 1 byte from/to odd address 1 byte from/to even address 16-bit word (both bytes) None (no byte enabled)

Introduction / Context:
The 8086 has a 16-bit data bus with byte enables: BHE# (high-byte enable, active low) and the least significant address line A0. Understanding their combinations clarifies how even and odd byte locations are accessed and when full 16-bit words are transferred.

Given Data / Assumptions:

• BHE in the pair (BHE, A0) is interpreted with 0 = asserted (enable high byte) and 1 = deasserted.
• A0 = 0 targets an even boundary (low byte), A0 = 1 targets an odd byte.
• Word transfer occurs when both low and high bytes are enabled simultaneously.

Concept / Approach:

Map each control combination to which byte lanes are enabled: low byte enable comes from A0 = 0; high byte enable comes from BHE = 0. Both enabled means a 16-bit word; only one enabled means a single byte at even or odd address; neither enabled means no transfer.

Step-by-Step Solution:

Verification / Alternative check:

Refer to 8086 memory interface timing diagrams: word accesses to even addresses assert both BHE# and A0=0; odd-byte access requires BHE# only; even-byte access uses A0=0 only.

Why Other Options Are Wrong:

Any mapping that assigns (0,0) to a single byte contradicts the 16-bit bus operation. Similarly, (1,1) must correspond to no active byte enable.

Common Pitfalls:

Forgetting that BHE is active low, or mixing up even/odd byte selection relative to A0. Also, assuming a word at an odd address is a single cycle; in fact, it typically requires two cycles.

Final Answer:

A-3, B-1, C-2, D-4