Decoder sizing for full output decoding How many 1-of-16 decoders are required to decode a full 7-bit binary input (128 unique outputs), assuming you may use an enable scheme to cascade devices?

Introduction / Context:
Address decoders translate binary input lines into one-hot outputs. A 1-of-16 decoder asserts exactly one of sixteen outputs based on 4 binary inputs (since 2^4 = 16). To decode N input bits fully into 2^N unique outputs, multiple decoder devices are cascaded using enable inputs. This question examines how to cover 7 input bits (128 outputs) using only 1-of-16 parts.

Given Data / Assumptions:

• Each 1-of-16 decoder handles 4 select inputs and has an enable input.
• Total inputs to decode: 7 bits → 128 distinct outputs.
• Cascading via enables is allowed (higher-order bits select which device is active).

Concept / Approach:

Partition the 7 bits into higher-order bits that choose which decoder is enabled and lower-order bits that feed the 4 select lines of each decoder. With 3 high-order bits you can choose among 2^3 = 8 devices; with 4 low-order bits you select one of 16 output lines on the enabled device. This yields 8 * 16 = 128 unique outputs.

Step-by-Step Solution:

Verification / Alternative check:

Count total outputs: 8 devices × 16 outputs/device = 128 outputs, exactly matching 2^7 possibilities. Timing and fanout requirements are satisfied because only one device is active at a time.

Why Other Options Are Wrong:

5, 6, 7 devices: insufficient, yielding at most 80, 96, or 112 outputs, respectively.

More than 8 devices are unnecessary; 8 is minimal with 1-of-16 parts because 2^7 / 16 = 8.

Common Pitfalls:

Attempting to cascade in series on the 4-bit inputs (which does not increase total outputs), or forgetting to reserve higher-order bits for device enables. Also, mixing up the roles of MSBs and LSBs can lead to duplicated or missing address ranges.

Final Answer:

8