Implementing a Digital One-Shot in HDL Which approach correctly describes how to implement a one-shot (single pulse per trigger event) using a hardware description language?

Introduction / Context:
A one-shot (monostable) generates a single, time-limited pulse for each qualifying trigger. In HDL for FPGAs or CPLDs, this is accomplished digitally using logic and flip-flops, not analog RC components. The design must respond once per edge and produce a controlled pulse width in clock cycles.

Given Data / Assumptions:

• A synchronous clock domain is available.
• The trigger input may be asynchronous and should be synchronized.
• Pulses are measured in integer clock cycles.

Concept / Approach:
Use an edge detector to convert a rising transition into a one-clock strobe, then start a counter or timer that holds the output HIGH for a programmed number of cycles. This ensures exactly one output pulse per trigger edge, regardless of how long the trigger level persists.

Step-by-Step Solution:
Synchronize trigger with two flip-flops to avoid metastability.Edge detect: pulse_start = sync_trig and (not sync_trig_d1).When pulse_start = 1, load a down-counter with N (pulse width in cycles).While counter > 0, assert output and decrement each clock.When counter reaches 0, deassert output and re-arm for the next edge.

Verification / Alternative check:
Simulation with long trigger levels and closely spaced edges shows one output pulse per 0→1 transition and a consistent pulse width of N cycles. Hardware timing reports confirm that the logic is purely digital and synthesizable.

Why Other Options Are Wrong:

• RC network in HDL: Analog RC cannot be described/synthesized meaningfully in standard FPGA logic.
• Generic “one-shot” library function: Not a universal primitive; vendors provide counters/timers instead.
• Level trigger: Produces level-sensitive behavior, not a single pulse per edge.

Common Pitfalls:
Failing to synchronize the trigger, neglecting edge detection (causing retriggers), or allowing retriggering while the pulse is active without explicit design intent.

Final Answer:
Apply the concept of a counter driven by a rising-edge detector to generate a fixed-width pulse.