Difficulty: Easy
Correct Answer: False
Explanation:
Introduction / Context:Sequential elements can have inputs that are either synchronous (qualified by a clock or gate) or asynchronous (acting immediately regardless of clock). Mislabeling these behaviors leads to design errors and timing violations. This question examines the common confusion surrounding gated SR flip-flops and asynchronous controls like PRE/CLR.
Given Data / Assumptions:
Concept / Approach:By definition, synchronous inputs affect the state only in relation to a gating signal or clock. In a gated SR flip-flop, S and R are evaluated only when the gate is active; otherwise the output holds. Asynchronous inputs bypass the gate and can change the state immediately at any time. Therefore, calling a gated SR flip-flop “asynchronous” because it responds immediately is incorrect.
Step-by-Step Solution:
Identify the enable/gate input: when inactive, S and R changes do not alter Q.When the gate is active, S/R can set or reset according to the truth table (this is synchronous operation).Asynchronous lines, if provided, act immediately regardless of the gate and are distinctly labeled.Hence, the statement claiming “gated SR are asynchronous” is false.Verification / Alternative check:Consult timing diagrams: setup/hold times are defined relative to the gate for S and R, confirming synchrony. PRE/CLR timing is specified independently, highlighting their asynchronous nature.
Why Other Options Are Wrong:
Common Pitfalls:Mixing up level-sensitive gating (synchronous) with asynchronous override signals; assuming any instantaneous response implies “asynchronous.”
Final Answer:False
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