FPGA hard-core reprogrammability claim: Evaluate the statement — “The hard-core portions of FPGAs are reprogrammable in the field.”

Introduction / Context:
Modern FPGAs include two types of resources: configurable fabric (LUTs, routing) and fixed-function “hard cores” (e.g., SERDES, PLLs, multipliers, sometimes embedded CPUs). This question ensures you can distinguish configuration of the fabric from the non-reprogrammable nature of hard silicon blocks.

Given Data / Assumptions:

• Hard cores are fixed at manufacture (mask-defined).
• Configurable logic is programmed via bitstreams.
• Field updates affect configuration, not transistor-level hard-macro design.

Concept / Approach:
“Reprogrammable” means you can change logic function after deployment. While the configurable fabric is indeed reprogrammable, hard cores are part of the chip’s permanent silicon. You can configure how those hard cores operate (e.g., set PLL multipliers), but you cannot reprogram their fundamental logic implementation in the field.

Step-by-Step Solution:

Verification / Alternative check:
Device datasheets separate “hard IP” (fixed) from “soft IP” (implemented in LUTs). Only soft IP changes with a new bitstream. Hard IP parameters are adjustable but the logic gates remain unchanged.

Why Other Options Are Wrong:

• Correct / only for DSP / partial reconfiguration: All confuse parameterization with reprogramming of hard silicon.
• JTAG fuses: Affect access and security, not the hard macro’s reprogrammability.

Common Pitfalls:
Equating “configurable” with “reprogrammable hard core”; assuming partial reconfiguration can alter hard IP composition; overlooking the difference between soft IP and hard IP.

Final Answer:
Incorrect