In typical microcomputers, what is the usual size order of on-chip or external cache memory?

Introduction / Context:
Cache memory bridges the speed gap between the CPU and main memory. Historically, in microcomputer contexts (especially classic microprocessors and embedded systems), cache was limited in size but very fast. Recognizing these typical magnitudes helps set realistic expectations for resource-constrained systems.

Given Data / Assumptions:

• We refer to “most microcomputers” in the classical/embedded sense, not modern desktop CPUs with multi-MB caches.
• Cache is smaller and faster than RAM.
• Technology generations vary; the question targets the usual small cache regime.

Concept / Approach:

Early and many embedded microcomputers provided small caches on the order of kilobytes to minimize die area and power while still improving performance; megabyte-scale caches are common in modern desktop/server CPUs but exceed the “microcomputer” notion in classical curricula.

Step-by-Step Solution:

Verification / Alternative check:

Examples: Many microcontrollers and older microprocessors (e.g., early ARM/MIPS cores) ship with L1 caches ranging from 1 KB to tens of KB per instruction/data side in basic configurations.

Why Other Options Are Wrong:

• Bytes: negligible benefit.
• Megabytes/Gigabytes: out of scope for “most microcomputers” in foundational courses.

Common Pitfalls:

Projecting modern desktop CPU cache sizes onto embedded/classic microcomputer contexts; confusing cache with RAM.

Final Answer:

a few kilobytes