Difficulty: Easy
Correct Answer: Correct
Explanation:
Introduction / Context:
Emitter-Coupled Logic (ECL) is a high-speed bipolar logic family that avoids transistor saturation by operating a differential amplifier stage. The heart of ECL is a long-tailed pair whose two transistors steer current between two collector load paths. This question tests whether you understand that ECL logic states (HIGH/LOW) arise from which side of the differential pair is conducting more, creating distinct voltage levels at the collectors and at the following emitter-follower outputs.
Given Data / Assumptions:
Concept / Approach:
ECL works by comparing an input to a reference using a differential pair. If the input exceeds the reference, one transistor draws more current; if it is less, the other side conducts. Because neither side saturates, charge storage is minimal and switching is very fast. The output logic levels are, therefore, a direct consequence of which branch of the differential pair is conducting more current through its load resistor(s).
Step-by-Step Solution:
Verification / Alternative check:
Sketch a basic ECL OR/NOR gate: the differential pair drives two collector nodes with load resistors; the higher-conducting side pulls its collector lower. Emitter followers add level shifting to standard ECL logic levels (negative rail referenced), confirming the mechanism.
Why Other Options Are Wrong:
Common Pitfalls:
Confusing the emitter-follower buffer with the decision element; assuming saturation-based logic like TTL; overlooking the role of the bias reference Vref in setting switching thresholds.
Final Answer:
Correct
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