Discussion
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- Question
Chip designers are always trying to increase the clock speed.
Options- A. True
- B. False
- Correct Answer
- True
- 1. In the digital clock project HDL, the 1 pps signal is used as a synchronous clock for all of the counters' stages, which are synchronously cascaded.
Options- A. True
- B. False Discuss
- 2. The output of the circuit in the given figure (a) at point X on figure (b) will be ________.
Options- A. 1.011 V
- B. 2.75 V
- C. ?1.011 V
- D. ?2.75 V Discuss
- 3. The most widespread application of ROMs is in the storage of data and program codes that must be available on power-down in the microprocessor-based systems. These data and program codes are called firmware because they are firmly stored in hardware.
Options- A. True
- B. False Discuss
- 4. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
Options- A. 74134
- B. LPM
- C. synchronous
- D. AHDL Discuss
- 5. A FIFO ________.
Options- A. allows data to be clocked in and out at different clock rates
- B. outputs the data in the same order that it was input
- C. can be used to smooth out bursts of data into a continuous stream
- D. All of the above Discuss
- 6. Subtraction of the 2's-complement system actually involves the operation of ________.
Options- A. multiplication
- B. subtraction
- C. addition
- D. division Discuss
- 7. The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.
Options- A. logic level
- B. flip-flop
- C. edge-detector circuit
- D. toggle detector Discuss
- 8. The process or sequence of all operations carried out to ultimately program a target device is called the ________.
Options- A. graphic entry
- B. LAB
- C. downloading
- D. design flow Discuss
- 9. The major advantage of dynamic RAM over static RAM is ________.
Options- A. cost
- B. speed
- C. storage density
- D. cost and storage density Discuss
- 10. A device used to display one or more digital signals so that they can be compared to expected timing diagrams for the signals is a:
Options- A. DMM
- B. spectrum analyzer
- C. logic analyzer
- D. frequency counter Discuss
More questions
Correct Answer: True
Correct Answer: ?2.75 V
Correct Answer: False
Correct Answer: LPM
Correct Answer: All of the above
Correct Answer: addition
Correct Answer: flip-flop
Correct Answer: design flow
Correct Answer: cost and storage density
Correct Answer: logic analyzer
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