Discussion
Home ‣ Digital Electronics ‣ Digital System Projects Using HDL Comments
- Question
In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.
Options- A. 0 hex
- B. 4 hex
- C. 8 hex
- D. F hex
- Correct Answer
- F hex
- 1. The interface of the stepper motor needs to operate in one of ________ mode(s).
Options- A. one
- B. two
- C. three
- D. four Discuss
- 2. A very critical dimension in project management is ________.
Options- A. cost
- B. skill
- C. time
- D. personnel Discuss
- 3. In the keypad encoder, the ________ activate(s) the freeze bit only when one column is low.
Options- A. NAND columns
- B. CASE structure
- C. freeze function
- D. BCD counter Discuss
- 4. In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.
Options- A. 1 pps
- B. 60 pps
- C. 100 pps
- D. 600 pps Discuss
- 5. Using one case construct inside another is known as ________.
Options- A. doping
- B. functioning
- C. freezing
- D. nesting Discuss
- 6. In the digital clock design, the hours section is different from the seconds and minutes section in that it never goes to ________.
Options- A. the 0 state
- B. 13
- C. the ring counter
- D. the BCD counter Discuss
- 7. One aspect of project planning and management is the selection of ________ that will best fit the application.
Options- A. hardware platform
- B. software
- C. personnel
- D. time Discuss
- 8. In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________.
Options- A. advanced BCD counters
- B. MOD-6 counters
- C. synchronous cascaded
- D. 1 pulse per second Discuss
- 9. Each ________, starting at the simplest level, should be built in HDL.
Options- A. subsystem
- B. block
- C. circuit
- D. function Discuss
- 10. In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.
Options- A. BCD counters
- B. system clock signal
- C. display register
- D. decoder/display Discuss
Digital System Projects Using HDL problems
Search Results
Correct Answer: four
Correct Answer: time
Correct Answer: CASE structure
Correct Answer: 60 pps
Correct Answer: nesting
Correct Answer: the 0 state
Correct Answer: hardware platform
Correct Answer: synchronous cascaded
Correct Answer: subsystem
Correct Answer: system clock signal
Comments
There are no comments.More in Digital Electronics:
Programming
Copyright ©CuriousTab. All rights reserved.