In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.
Options
A. set
B. reset
C. toggle
D. clear
Correct Answer
toggle
More questions
1. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
8. Using the CPLD design environment, we can simulate any combinations of inputs and observe the resulting output to check for proper circuit operation.