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Home ‣ Digital Electronics ‣ Digital System Projects Using HDL Comments
  • Question

  • In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the edge trigger clock moves the display to 12:00:00.


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    • Digital System Projects Using HDL problems

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    • 1. In the digital clock project, the ENT input and RCO output can be used for synchronous counter cascading.

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    • A. True
    • B. False
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    • 2. In the keypad HDL encoder, as long as all columns are high the ring counter is enabled and counting.

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    • A. True
    • B. False
      • Discuss
    • 3. In the digital clock project, a MOD-60 BCD counter is made from a MOD-10 counter cascaded to a MOD-6 BCD counter.

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    • A. True
    • B. False
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    • 4. In the keypad HDL encoder, the ts bit array represents a tristate buffer.

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    • A. True
    • B. False
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    • 5. In the keypad HDL encoder, NANDing of the columns is used to activate the freeze bit.

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    • A. True
    • B. False
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    • 6. In the keypad HDL encoder, after releasing a key the ring counter resumes its counting sequence.

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    • A. True
    • B. False
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    • 7. In the frequency counter, a pulse shaper block is needed to ensure that the unknown signal, whose frequency is to be measured, will be compatible with the clock input for the counter block.

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    • A. True
    • B. False
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    • 8. The frequency counter measures frequency by enabling a counter to count the number of pulses of the incoming waveform during a precisely specified period of time called the sampling time.

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    • A. True
    • B. False
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    • 9. The full-step sequence always has two coils of the stepper motor energized in any state of the sequence and typically causes 30° of shaft rotation per step.

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    • A. True
    • B. False
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    • 10. In the digital clock project, the AHDL block codes are connected using graphic design files.

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    • A. True
    • B. False
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