Discussion
Home ‣ Digital Electronics ‣ Programmable Logic Device Comments
- Question
The Boolean expression AB + CD is an example of ________.
Options- A. PAL
- B. GAL
- C. SOP
- D. POS
- Correct Answer
- SOP
- 1. Full custom ICs can operate at ________ and require the ________.
Options- A. lowest speed, largest die area
- B. lowest speed, smallest die area
- C. highest speed, largest die area
- D. highest speed, smallest die area Discuss
- 2. The process or sequence of all operations carried out to ultimately program a target device is called the ________.
Options- A. graphic entry
- B. LAB
- C. downloading
- D. design flow Discuss
- 3. The major structures in the MAX7000S are the ________ and ________.
Options- A. LUT, PIA
- B. FMUX, LAB
- C. LAB, PIA
- D. LUT, FMUX Discuss
- 4. The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.
Options- A. GAL
- B. SOP
- C. PROM
- D. LAB Discuss
- 5. An application program in the development software package that controls the operation of the software is called a ________.
Options- A. compiler
- B. bed-of-nails
- C. boundary scan
- D. primitive Discuss
- 6. The EPM 7128S is a(n) ________ device.
Options- A. PLD
- B. JTAG
- C. EEPROM
- D. ISP Discuss
- 7. The ________ is the most popular standard logic device family today.
Options- A. TTL
- B. CMOS
- C. ECL
- D. None of the above Discuss
- 8. In a MAX7000S device, when an I/O pin is configured as an input, the associated macrocell can be used for ________.
Options- A. buried logic
- B. another output
- C. extra speed
- D. in-system testing Discuss
- 9. The SPLD classification includes the ________ PLD devices.
Options- A. earliest
- B. smallest
- C. largest
- D. newest Discuss
- 10. Four subcategories of ASIC devices are available to create digital systems. These are PLDs, gate arrays, standard cells, and ________.
Options- A. HCPLDs
- B. full custom
- C. GAL
- D. FPLDs Discuss
Programmable Logic Device problems
Search Results
Correct Answer: highest speed, smallest die area
Correct Answer: design flow
Correct Answer: LAB, PIA
Correct Answer: PROM
Correct Answer: compiler
Correct Answer: ISP
Correct Answer: CMOS
Correct Answer: buried logic
Correct Answer: earliest
Correct Answer: full custom
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