Discussion
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- Question
The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.
Options- A. GAL
- B. SOP
- C. PROM
- D. LAB
- Correct Answer
- PROM
- 1. An application program in the development software package that controls the operation of the software is called a ________.
Options- A. compiler
- B. bed-of-nails
- C. boundary scan
- D. primitive Discuss
- 2. The MAX+PLUS II compiler will automatically program a macrocell to borrow up to ________ product terms from each of the 3 adjacent macrocells in the same LAB.
Options- A. 4
- B. 5
- C. 6
- D. 7 Discuss
- 3. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer interconnect that is used to connect internal logic modules is called a ________.
Options- A. bed-of-nails
- B. boundary scan
- C. CLB
- D. CPLD Discuss
- 4. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
Options- A. AND array
- B. Look-up table
- C. OR array
- D. AND and OR array Discuss
- 5. ________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.
Options- A. TTL
- B. CMOS
- C. ECL
- D. None of the above Discuss
- 6. The major structures in the MAX7000S are the ________ and ________.
Options- A. LUT, PIA
- B. FMUX, LAB
- C. LAB, PIA
- D. LUT, FMUX Discuss
- 7. The process or sequence of all operations carried out to ultimately program a target device is called the ________.
Options- A. graphic entry
- B. LAB
- C. downloading
- D. design flow Discuss
- 8. Full custom ICs can operate at ________ and require the ________.
Options- A. lowest speed, largest die area
- B. lowest speed, smallest die area
- C. highest speed, largest die area
- D. highest speed, smallest die area Discuss
- 9. The Boolean expression AB + CD is an example of ________.
Options- A. PAL
- B. GAL
- C. SOP
- D. POS Discuss
- 10. The EPM 7128S is a(n) ________ device.
Options- A. PLD
- B. JTAG
- C. EEPROM
- D. ISP Discuss
Programmable Logic Device problems
Search Results
Correct Answer: compiler
Correct Answer: 5
Correct Answer: CLB
Correct Answer: Look-up table
Correct Answer: TTL
Correct Answer: LAB, PIA
Correct Answer: design flow
Correct Answer: highest speed, smallest die area
Correct Answer: SOP
Correct Answer: ISP
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