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Home Digital Electronics Programmable Logic Device Comments

  • Question
  • In the GAL16V8, the ________ selects the signal that is fed back into the input matrix.


  • Options
  • A. FMUX
  • B. OMUX
  • C. PTMUX
  • D. TSMUX

  • Correct Answer
  • FMUX 


  • Programmable Logic Device problems


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    • 1. The final step in a design flow in which the logic design is implemented in the target device is called ________.

    • Options
    • A. design entry
    • B. simulation
    • C. downloading
    • D. compiling
    • Discuss
    • 2. All inputs to the MAX7000S device and all macrocell outputs feed the ________.

    • Options
    • A. LUT
    • B. PIA
    • C. LAB
    • D. PIA and LAB
    • Discuss
    • 3. In a FLEX10K device, the carry chain provides a fast carry forward function between ________.

    • Options
    • A. LUTs
    • B. EABs
    • C. LEs
    • D. LABs
    • Discuss
    • 4. In the GAL16V8, the ________ controls the tristate buffer's enable input.

    • Options
    • A. FMUX
    • B. OMUX
    • C. PTMUX
    • D. TMUX
    • Discuss
    • 5. In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.

    • Options
    • A. a dot
    • B. a bus
    • C. a single line
    • D. 4 inputs
    • Discuss
    • 6. The flexibility of the GAL16V8 is in its ________.

    • Options
    • A. AND/OR array
    • B. D flip-flops
    • C. programmable output logic macro cells
    • D. EEPROM
    • Discuss
    • 7. Using a hardware solution for a digital system is always ________ than a software solution.

    • Options
    • A. slower
    • B. harder
    • C. easier
    • D. faster
    • Discuss
    • 8. ________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.

    • Options
    • A. TTL
    • B. CMOS
    • C. ECL
    • D. None of the above
    • Discuss
    • 9. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.

    • Options
    • A. AND array
    • B. Look-up table
    • C. OR array
    • D. AND and OR array
    • Discuss
    • 10. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer interconnect that is used to connect internal logic modules is called a ________.

    • Options
    • A. bed-of-nails
    • B. boundary scan
    • C. CLB
    • D. CPLD
    • Discuss


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