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Home Digital Electronics Programmable Logic Device Comments

  • Question
  • A macrocell is ________.


  • Options
  • A. part of a PAL or GAL
  • B. a type of one-time programmable SPLD
  • C. an example of intellectual property
  • D. a logic array block

  • Correct Answer
  • part of a PAL or GAL 


  • Programmable Logic Device problems


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    • 1. FLEX10K devices are generally classified as ________.

    • Options
    • A. PLDs
    • B. FPGAs
    • C. HCPLDs
    • D. CPLDs
    • Discuss
    • 2. The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.

    • Options
    • A. SRAM
    • B. flash
    • C. antifuse
    • D. SRAM and flash
    • Discuss
    • 3. Design costs for standard cell ASICs are ________ those for MPGAs.

    • Options
    • A. lower than
    • B. about the same as
    • C. higher than
    • D. none of the above
    • Discuss
    • 4. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.

    • Options
    • A. 100-pin
    • B. 120-pin
    • C. 140-pin
    • D. 160-pin
    • Discuss
    • 5. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.

    • Options
    • A. asynchronous reset, synchronous preset
    • B. asynchronous preset, synchronous reset
    • C. asynchronous clear, synchronous set
    • D. asynchronous set, synchronous clear
    • Discuss
    • 6. In the MAX7000S device up to ________ signals can feed each LAB from the PIA.

    • Options
    • A. 0
    • B. 18
    • C. 36
    • D. 72
    • Discuss
    • 7. A GAL22V10 ________.

    • Options
    • A. has up to 32 inputs and 10 outputs
    • B. is a type of SPLD
    • C. has 10 inputs and 22 outputs
    • D. is downloadable from the manufacturer's Web site
    • Discuss
    • 8. A method for the automated testing of printed circuit boards is called a(n) ________.

    • Options
    • A. bed-of-nails
    • B. LUT
    • C. CLB
    • D. CPLD
    • Discuss
    • 9. In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.

    • Options
    • A. a dot
    • B. a bus
    • C. a single line
    • D. 4 inputs
    • Discuss
    • 10. In the GAL16V8, the ________ controls the tristate buffer's enable input.

    • Options
    • A. FMUX
    • B. OMUX
    • C. PTMUX
    • D. TMUX
    • Discuss


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