Design costs for standard cell ASICs are ________ those for MPGAs. lower than ab

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Question
Design costs for standard cell ASICs are ________ those for MPGAs.
Options
A. lower than
B. about the same as
C. higher than
D. none of the above

Correct Answer

higher than

More questions

1. A transducer is a device that:
Options
A. converts a physical variable to an electrical variable
B. converts analog data to meaningful data
C. controls a physical variable
D. stores digital data and then processes that data according to a set of specified instructions

3. What must be done to interface CMOS to TTL?
Options
A. A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL.
B. As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the CMOS is limited to two TTL gates.
C. A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates.
D. The two series cannot be interfaced without the use of special interface buffers designed for that purpose, such as the open-collector buffers.

4. Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?
Options
A. 0
B. 1
C. 2
D. 3

7. The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
Options
A. a steady LOW
B. a steady HIGH
C. an undefined level
D. pulses

8. Shifting a binary number to the left by one position is equivalent to ________.
Options
A. multiplying by two
B. multiplying by four
C. dividing by two
D. dividing by four

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