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- Question
Design costs for standard cell ASICs are ________ those for MPGAs.
Options- A. lower than
- B. about the same as
- C. higher than
- D. none of the above
- Correct Answer
- higher than
- 1. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.
Options- A. 100-pin
- B. 120-pin
- C. 140-pin
- D. 160-pin Discuss
- 2. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.
Options- A. asynchronous reset, synchronous preset
- B. asynchronous preset, synchronous reset
- C. asynchronous clear, synchronous set
- D. asynchronous set, synchronous clear Discuss
- 3. The distinction between CPLDs and FPGAs is ________.
Options- A. well known
- B. very small
- C. often fuzzy
- D. very large Discuss
- 4. Gated arrays are ________ circuits that offer hundreds of thousands of gates.
Options- A. VLSI
- B. full custom
- C. LSI
- D. ULSI Discuss
- 5. Most complex digital designs include ________.
Options- A. standard logic devices
- B. ASIC devices
- C. microprocessor/DSP devices
- D. a mix of different hardware categories Discuss
- 6. The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.
Options- A. SRAM
- B. flash
- C. antifuse
- D. SRAM and flash Discuss
- 7. FLEX10K devices are generally classified as ________.
Options- A. PLDs
- B. FPGAs
- C. HCPLDs
- D. CPLDs Discuss
- 8. A macrocell is ________.
Options- A. part of a PAL or GAL
- B. a type of one-time programmable SPLD
- C. an example of intellectual property
- D. a logic array block Discuss
- 9. In the MAX7000S device up to ________ signals can feed each LAB from the PIA.
Options- A. 0
- B. 18
- C. 36
- D. 72 Discuss
- 10. A GAL22V10 ________.
Options- A. has up to 32 inputs and 10 outputs
- B. is a type of SPLD
- C. has 10 inputs and 22 outputs
- D. is downloadable from the manufacturer's Web site Discuss
Programmable Logic Device problems
Search Results
Correct Answer: 160-pin
Correct Answer: asynchronous reset, synchronous preset
Correct Answer: often fuzzy
Correct Answer: ULSI
Correct Answer: a mix of different hardware categories
Correct Answer: SRAM
Correct Answer: FPGAs
Correct Answer: part of a PAL or GAL
Correct Answer: 36
Correct Answer: is a type of SPLD
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