CuriousTab
Search
CuriousTab
Home
Aptitude
Computer
C Programming
C# Programming
C++ Programming
Database
Java Programming
Networking
Engineering
Biochemical Engineering
Biochemistry
Biotechnology
Chemical Engineering
Civil Engineering
Computer Science
Digital Electronics
Electrical Engineering
Electronics
Electronics and Communication Engineering
Mechanical Engineering
Microbiology
Technical Drawing
GK
Current Affairs
General Knowledge
Reasoning
Data Interpretation
Logical Reasoning
Non Verbal Reasoning
Verbal Ability
Verbal Reasoning
Exams
AIEEE
Bank Exams
CAT
GATE
IIT JEE
TOEFL
Jobs
Analyst
Bank PO
Database Administrator
IT Trainer
Network Engineer
Project Manager
Software Architect
Discussion
Home
‣
Digital Electronics
‣
Programmable Logic Device
Comments
Question
In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.
Options
A. asynchronous reset, synchronous preset
B. asynchronous preset, synchronous reset
C. asynchronous clear, synchronous set
D. asynchronous set, synchronous clear
Correct Answer
asynchronous reset, synchronous preset
Programmable Logic Device problems
Search Results
1. The distinction between CPLDs and FPGAs is ________.
Options
A. well known
B. very small
C. often fuzzy
D. very large
Show Answer
Scratch Pad
Discuss
Correct Answer: often fuzzy
2. Gated arrays are ________ circuits that offer hundreds of thousands of gates.
Options
A. VLSI
B. full custom
C. LSI
D. ULSI
Show Answer
Scratch Pad
Discuss
Correct Answer: ULSI
3. Most complex digital designs include ________.
Options
A. standard logic devices
B. ASIC devices
C. microprocessor/DSP devices
D. a mix of different hardware categories
Show Answer
Scratch Pad
Discuss
Correct Answer: a mix of different hardware categories
4. The field programmable logic array was the first ________ programmable logic device.
Options
A. understandable
B. logic array
C. multifunction
D. nonmemory
Show Answer
Scratch Pad
Discuss
Correct Answer: nonmemory
5. The GAL16V8 has architecture that is very similar to the ________ device.
Options
A. PAL
B. PROM
C. PLD
D. SPLD
Show Answer
Scratch Pad
Discuss
Correct Answer: PAL
6. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.
Options
A. 100-pin
B. 120-pin
C. 140-pin
D. 160-pin
Show Answer
Scratch Pad
Discuss
Correct Answer: 160-pin
7. Design costs for standard cell ASICs are ________ those for MPGAs.
Options
A. lower than
B. about the same as
C. higher than
D. none of the above
Show Answer
Scratch Pad
Discuss
Correct Answer: higher than
8. The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.
Options
A. SRAM
B. flash
C. antifuse
D. SRAM and flash
Show Answer
Scratch Pad
Discuss
Correct Answer: SRAM
9. FLEX10K devices are generally classified as ________.
Options
A. PLDs
B. FPGAs
C. HCPLDs
D. CPLDs
Show Answer
Scratch Pad
Discuss
Correct Answer: FPGAs
10. A macrocell is ________.
Options
A. part of a PAL or GAL
B. a type of one-time programmable SPLD
C. an example of intellectual property
D. a logic array block
Show Answer
Scratch Pad
Discuss
Correct Answer: part of a PAL or GAL
Comments
There are no comments.
Enter a new Comment
Save
More in Digital Electronics:
Boolean Algebra and Logic Simplification
Code Converters and Multiplexers
Combinational Logic Analysis
Combinational Logic Circuits
Computers
Counters
Describing Logic Circuits
Digital Arithmetic Operations and Circuits
Digital Concepts
Digital Design
Digital Signal Processing
Digital System Projects Using HDL
Ex-OR and Ex-NOR Gates
Flip-Flops
Integrated-Circuit Logic Families
Integrated Circuit Technologies
Interfacing to the Analog World
Logic Families and Their Characteristics
Logic Gates
Memory and Storage
Microprocessor Fundamentals
MSI Logic Circuits
Multivibrators and 555 Timer
Number Systems and Codes
Programmable Logic Device
Shift Registers
Signals and Switches
The 8051 Microcontroller