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Home Digital Electronics Programmable Logic Device Comments

  • Question
  • Most complex digital designs include ________.


  • Options
  • A. standard logic devices
  • B. ASIC devices
  • C. microprocessor/DSP devices
  • D. a mix of different hardware categories

  • Correct Answer
  • a mix of different hardware categories 


  • Programmable Logic Device problems


    Search Results


    • 1. The field programmable logic array was the first ________ programmable logic device.

    • Options
    • A. understandable
    • B. logic array
    • C. multifunction
    • D. nonmemory
    • Discuss
    • 2. The GAL16V8 has architecture that is very similar to the ________ device.

    • Options
    • A. PAL
    • B. PROM
    • C. PLD
    • D. SPLD
    • Discuss
    • 3. A complex programmable logic device that consists of multiple SPLD arrays with programmable interconnections is called a ________.

    • Options
    • A. bed-of-nails
    • B. boundary scan
    • C. CLB
    • D. CPLD
    • Discuss
    • 4. The Boolean expression (A + B)(C + D) is an example of ________.

    • Options
    • A. LAB
    • B. LUT
    • C. SOP
    • D. POS
    • Discuss
    • 5. The major digital system categories include Boolean logic, ASICs, and microprocessor/DSP devices.

    • Options
    • A. True
    • B. False
    • Discuss
    • 6. Gated arrays are ________ circuits that offer hundreds of thousands of gates.

    • Options
    • A. VLSI
    • B. full custom
    • C. LSI
    • D. ULSI
    • Discuss
    • 7. The distinction between CPLDs and FPGAs is ________.

    • Options
    • A. well known
    • B. very small
    • C. often fuzzy
    • D. very large
    • Discuss
    • 8. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.

    • Options
    • A. asynchronous reset, synchronous preset
    • B. asynchronous preset, synchronous reset
    • C. asynchronous clear, synchronous set
    • D. asynchronous set, synchronous clear
    • Discuss
    • 9. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.

    • Options
    • A. 100-pin
    • B. 120-pin
    • C. 140-pin
    • D. 160-pin
    • Discuss
    • 10. Design costs for standard cell ASICs are ________ those for MPGAs.

    • Options
    • A. lower than
    • B. about the same as
    • C. higher than
    • D. none of the above
    • Discuss


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