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Home ‣ Digital Electronics ‣ Programmable Logic Device Comments
  • Question

  • VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • True 

    • Programmable Logic Device problems

    Search Results

    • 1. The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. Gate arrays are ULSI circuits that offer hundreds of thousands of gates.

    • Options
    • A. True
    • B. False
      • Discuss
    • 3. The schematic editor allows you to connect with predefined logic symbols.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. In a PLD, a blown fuse at an OR gate is a LOW and a blown fuse at an AND gate is a HIGH.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. The GAL chip uses an EEPROM array that is erasable and reprogrammable at least 1000 times.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. The JTAG signals are named TDI, TDO, TMS, and TCK.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. A GAL is a programmable/reprogrammable PAL.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. Schematic capture is a process performed by PLD software.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. An expensive form of programmable logic is SPLD.

    • Options
    • A. True
    • B. False
      • Discuss

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