Assume you want to determine the timing diagram for a 4-bit counter using an osc

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Question
Assume you want to determine the timing diagram for a 4-bit counter using an oscilloscope. The best choice for an oscilloscope trigger signal is ________.
Options
A. the most significant bit (MSB)
B. the least significant bit (LSB)
C. the clock signal
D. from a composite of the MSB and LSB

Correct Answer

the clock signal

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2. Many parallel counters use ________ presetting whereby the counter is preset on the active transition of the same clock signal that is used for counting.
Options
A. feedback
B. synchronous
C. ripple
D. asynchronous

4. One method of troubleshooting involves ________ the circuit under test with a ________ or ________ and then observing the output to check for proper bit patterns.
Options
A. checking, voltmeter, ohmmeter
B. exercising, stimulus, test pattern
C. testing, scope, logic analyzer
D. smashing, hammer, axe

7. Assume a 4-bit ripple counter has a failure in the second flip-flop such that it "locks up." The third and fourth stages will ________.
Options
A. continue to count with correct outputs
B. continue to count but have incorrect outputs
C. stop counting
D. turn into molten silicon

9. A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because ________.
Options
A. it is a random event
B. it occurs less frequently than the normal decoded output
C. it is very fast
D. all of the above

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