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  • Question

  • An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________.


  • Options
  • A. taking the output on the other side of the flip-flops (An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be c instead of Q)
  • B. clocking of each succeeding flip-flop from the other side (An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be c instead of Q)
  • C. changing the flip-flops to trailing edge triggering
  • D. all of the above

  • Correct Answer
  • all of the above 

    • Counters problems

    Search Results

    • 1. It is a characteristic of ring counters that the ________ equal to the number of flip-flops in the register.

    • Options
    • A. number of invalid states is
    • B. number of CASE statements is
    • C. modulus is
    • D. other states are
      • Discuss
    • 2. A(n) ________ one-shot starts a pulse in response to a trigger and will restart the internal pulse timer every time a subsequent trigger edge occurs before the pulse is complete.

    • Options
    • A. non-retriggerable
    • B. retriggerable
    • C. high-level triggered
    • D. edge-triggered
      • Discuss
    • 3. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

    • Options
    • A. 74134
    • B. LPM
    • C. synchronous
    • D. AHDL
      • Discuss
    • 4. A decade counter will count through decimal ________.

    • Options
    • A. 10
    • B. 9
    • C. 15
    • D. 0
      • Discuss
    • 5. In order to check the CLR function of a counter, ________.

    • Options
    • A. apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
    • B. ground the CLR input and check to be sure that all of the Q outputs are LOW
    • C. connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
    • D. connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling
      • Discuss
    • 6. A sequential circuit design is used to ________.

    • Options
    • A. count up
    • B. count down
    • C. decode an end count
    • D. count in a random order
      • Discuss
    • 7. ________ is the output frequency of the counter shown below.


    • Options
    • A. 4 MHz
    • B. 20 kHz
    • C. 210.5 kHz
    • D. 800 Hz
      • Discuss
    • 8. One method of troubleshooting involves ________ the circuit under test with a ________ or ________ and then observing the output to check for proper bit patterns.

    • Options
    • A. checking, voltmeter, ohmmeter
    • B. exercising, stimulus, test pattern
    • C. testing, scope, logic analyzer
    • D. smashing, hammer, axe
      • Discuss
    • 9. The given circuit represents a(n) ________.


    • Options
    • A. four-bit binary counter
    • B. asynchronous BCD decade counter
    • C. synchronous BCD decade counter
    • D. BCD-to-decimal decoder
      • Discuss
    • 10. Many parallel counters use ________ presetting whereby the counter is preset on the active transition of the same clock signal that is used for counting.

    • Options
    • A. feedback
    • B. synchronous
    • C. ripple
    • D. asynchronous
      • Discuss

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