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  • Question

  • In order to check the CLR function of a counter, ________.


  • Options
  • A. apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
  • B. ground the CLR input and check to be sure that all of the Q outputs are LOW
  • C. connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
  • D. connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling

  • Correct Answer
  • apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state 

    • Counters problems

    Search Results

    • 1. The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.


    • Options
    • A. multiplexing, 1
    • B. parallel-to-serial conversion, 0
    • C. demultiplexing, 0
    • D. parallel-to-serial conversion, HIGH
      • Discuss
    • 2. The duty cycle of the most significant bit from a 4-bit (0?9) BCD counter is ________.

    • Options
    • A. 10%
    • B. 20%
    • C. 50%
    • D. 80%
      • Discuss
    • 3. A BCD counter has ________ states.

    • Options
    • A. 8
    • B. 9
    • C. 10
    • D. 11
      • Discuss
    • 4. A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.

    • Options
    • A. J and K inputs must both = 0
    • B. J must be 0, K doesn't matter
    • C. J doesn't matter, K must = 0
    • D. J must be 0 and K must be 1
      • Discuss
    • 5. The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.

    • Options
    • A. 8
    • B. 15
    • C. 16
    • D. 32
      • Discuss
    • 6. A decade counter will count through decimal ________.

    • Options
    • A. 10
    • B. 9
    • C. 15
    • D. 0
      • Discuss
    • 7. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

    • Options
    • A. 74134
    • B. LPM
    • C. synchronous
    • D. AHDL
      • Discuss
    • 8. A(n) ________ one-shot starts a pulse in response to a trigger and will restart the internal pulse timer every time a subsequent trigger edge occurs before the pulse is complete.

    • Options
    • A. non-retriggerable
    • B. retriggerable
    • C. high-level triggered
    • D. edge-triggered
      • Discuss
    • 9. It is a characteristic of ring counters that the ________ equal to the number of flip-flops in the register.

    • Options
    • A. number of invalid states is
    • B. number of CASE statements is
    • C. modulus is
    • D. other states are
      • Discuss
    • 10. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________.

    • Options
    • A. taking the output on the other side of the flip-flops ( instead of Q)
    • B. clocking of each succeeding flip-flop from the other side ( instead of Q)
    • C. changing the flip-flops to trailing edge triggering
    • D. all of the above
      • Discuss

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