Discussion
Home ‣ Digital Electronics ‣ Counters Comments
- Question
The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.
Options- A. multiplexing, 1
- B. parallel-to-serial conversion, 0
- C. demultiplexing, 0
- D. parallel-to-serial conversion, HIGH
- Correct Answer
- parallel-to-serial conversion, 0
- 1. The duty cycle of the most significant bit from a 4-bit (0?9) BCD counter is ________.
Options- A. 10%
- B. 20%
- C. 50%
- D. 80% Discuss
- 2. A BCD counter has ________ states.
Options- A. 8
- B. 9
- C. 10
- D. 11 Discuss
- 3. A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.
Options- A. J and K inputs must both = 0
- B. J must be 0, K doesn't matter
- C. J doesn't matter, K must = 0
- D. J must be 0 and K must be 1 Discuss
- 4. The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.
Options- A. 8
- B. 15
- C. 16
- D. 32 Discuss
- 5. Modulus refers to ________.
Options- A. a method used to fabricate decade counter units
- B. the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
- C. an input on a counter that is used to set the counter state, such as UP/DOWN
- D. the maximum number of states in a counter sequence Discuss
- 6. In order to check the CLR function of a counter, ________.
Options- A. apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
- B. ground the CLR input and check to be sure that all of the Q outputs are LOW
- C. connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
- D. connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling Discuss
- 7. A decade counter will count through decimal ________.
Options- A. 10
- B. 9
- C. 15
- D. 0 Discuss
- 8. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
Options- A. 74134
- B. LPM
- C. synchronous
- D. AHDL Discuss
- 9. A(n) ________ one-shot starts a pulse in response to a trigger and will restart the internal pulse timer every time a subsequent trigger edge occurs before the pulse is complete.
Options- A. non-retriggerable
- B. retriggerable
- C. high-level triggered
- D. edge-triggered Discuss
- 10. It is a characteristic of ring counters that the ________ equal to the number of flip-flops in the register.
Options- A. number of invalid states is
- B. number of CASE statements is
- C. modulus is
- D. other states are Discuss
Counters problems
Search Results
Correct Answer: 20%
Correct Answer: 10
Correct Answer: J must be 0, K doesn't matter
Correct Answer: 15
Correct Answer: the maximum number of states in a counter sequence
Correct Answer: apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
Correct Answer: 9
Correct Answer: LPM
Correct Answer: retriggerable
Correct Answer: modulus is
Comments
There are no comments.More in Digital Electronics:
Programming
Copyright ©CuriousTab. All rights reserved.